ASIC Physical Design Engineer - New College Grad 2027
Company: NVIDIA
Role summary
ASIC Physical Design Engineer - New College Grad 2027 is a full-time role at NVIDIA in Shanghai, Shanghai, China (on-site). Posted 2026-10-25. Experience level: 0-2. No degree required.
- Job title
- ASIC Physical Design Engineer - New College Grad 2027
- Company
- NVIDIA
- Location
- Shanghai, Shanghai, China
- Work arrangement
- on-site
- Employment type
- full-time
- Category
- Software Engineering
- Experience level
- 0-2
- Degree required
- No
- Date posted
- 2026-10-25
You’ll have the chance to kick off your career at the forefront of the AI revolution by helping design the high-performance chips that power the world’s most advanced computing systems. It’s an incredible opportunity for someone who loves solving complex engineering puzzles to grow alongside a team that is literally defining the future of hardware.
Job description
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
With the continuous improvement of chip technology, design scale and performance/power ratio, the physical design of digital chips is facing outstanding challenges in high frequency, low power consumption and multiple applications. High efficiency, high quality of the implementation of the construction chip is the guarantee of the company's competitiveness. As an ASIC-PD engineer at NVIDIA, you'll be responsible for the stage from RTL frozen to tape out, include synthesis, formal verification, constraints definition, timing closure/sign off, study on the timing impact of process and related methodology work. You will face the biggest challenge based on the most advanced process on building chips in the world.
What you'll be doing:
Chip integration and netlist generation
Synthesis
RTL/netlist quality check
Formal Verification
Constraints creation and validation, timing budget.
Work with ASIC team to analyze/resolve special timing issues.
Cross-Team collaboration to implement chip partitioning and floorplan
Work in conjunction with PR engineers to achieve timing closure for both partition and full chip level
Achieve special mode timing closure, such as io, test, clock, async etc.
Function eco creation
Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout)
Flow automation development for above areas
Methodology in any of above areas.
What we need to see:
MS in EE or Microelectronics (or equivalent experience)
Project experience in IC design implementation
Courses taken in circuit design, digital design
Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is helpful
Proficient user of Python or TCL is helpful
Proficient in English reading and writing
NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!
Apply for ASIC Physical Design Engineer - New College Grad 2027 at NVIDIA